1. Field of the Disclosure
The present disclosure relates to a sense circuit used in a semiconductor device, and particularly relates to a sense circuit for suitably compensating for temperature dependence of the threshold voltage in a MOS (metal-oxide-semiconductor) transistor that constitutes a sense circuit, to a temperature compensation method for a sense circuit, and to a data processing system.
2. Description of Related Art
It is known that the threshold voltage in a MOS transistor used in a semiconductor device generally varies depending on temperature, and that the temperature margin of the circuit is thereby reduced. Numerous techniques have therefore been proposed to compensate for this temperature dependence.
The technique disclosed in Japanese Patent Application Laid-Open No. S58-168310, for example, relates to a sense amplifier circuit in MOS static memory, and the on output level of the output buffer of the sense amplifier circuit is stabilized using a differential amplifier by varying the output level of the differential amplifier according to temperature.
The technique disclosed in Japanese Patent Application Laid-Open No. 2000-307391 relates to control of the input threshold value of a voltage comparator. The disclosed voltage comparator includes a PMOS (p-channel metal-oxide-semiconductor) transistor in which a signal is inputted to the gate, the drain is connected to a power supply, and the source is connected to an output line, and two NMOS (n-channel metal-oxide-semiconductor) transistors connected in series between the output line and the ground, wherein the NMOS transistors are arranged in a column, a signal is inputted to the gate of one NMOS transistor connected in series, and a fixed control voltage is inputted to the gate of the other NMOS transistor. This technique emphasizes the fact that the conductance of a MOS transistor is uniquely related to the gate voltage, and supposing that the circuit described above is an equivalent circuit configured from a resistor, attempts to control the input threshold of the voltage comparator by adjusting the individual gate voltages fed to each MOS transistor and varying the conductance.
FIG. 19 is a diagram showing the threshold voltage distribution, i.e., the allowable range of manufacturing variation, of a MOS transistor in a case in which temperature compensation is not applied in a sense circuit used in DRAM (dynamic random access memory) having a hierarchical bit line structure. The vertical axis indicates voltage, and the bar graph on the left side indicates the memory cell node potential when the power supply potential VDD is 1 V (volt). The bit line pre-charge potential is set to 0 V.
It is usually the case in DRAM that high data of 1 V and low data of 0 V are written in a memory cell node, but loss occurs due to leakage, inadequate writing, or the like. In this example, the high data is 0.7 V and the low data is 0.2 V due to loss. When a word line is high, and a memory cell is selected, a signal voltage is read to the bit line by the transfer of charge between the bit line parasitic capacitor Cb and the capacitor Cs of the memory cell. This read signal voltage occurs in the bit line as the voltage of the memory cell node minus the portion accounted for by the transfer ratio Cs/(Cs+Cb). The transfer ratio is 0.7 in this example.
The signal voltage read to the bit line undergoes further loss due to noise during reading, and in this example, the high read signal voltage is 0.45 V, and the low read signal voltage is about 0.18 V. This difference in voltage is amplified by a MOS transistor and converted to a drain current difference, and in order for a global bit line sense circuit to properly determine high or low for the difference of the global bit line discharge time, there must be a determination margin between the lower limit of the high read voltage and the upper limit of the MOS transistor threshold voltage distribution, and between the upper limit of the low read voltage and the lower limit of the MOS transistor threshold voltage distribution.
As previously mentioned, since the threshold voltage of a MOS transistor generally varies depending on the temperature, the distribution of the threshold voltage due to manufacturing variation must be kept small so as to be able to accommodate variation due to temperature dependence in order to ensure the abovementioned determination margin at the operating compensation temperature, which in this example is between 0° C. and 100° C. (Celsius).